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Download CMOS VLSI Engineering: Silicon-on-Insulator (SOI) by James B. Kuo, Ker-Wei Su PDF

By James B. Kuo, Ker-Wei Su

Silicon-On-Insulator (SOI) CMOS know-how has been considered as one other significant expertise for VLSI as well as bulk CMOS expertise. because of the buried oxide constitution, SOI know-how bargains enhanced CMOS units with larger velocity, excessive density, and diminished moment order results for deep-submicron low-voltage, low-power VLSI circuits purposes. as well as VLSI functions, and thanks to its awesome homes, SOI expertise has been used to achieve conversation circuits, microwave units, BICMOS units, or even fiber optics functions.
CMOS VLSI Engineering: Silicon-On-Insulator addresses 3 key elements in engineering SOI CMOS VLSI - processing know-how, machine modelling, and circuit designs are all lined with their mutual interactions. ranging from the SOI CMOS processing expertise and the SOI CMOS electronic and analog circuits, behaviors of the SOI CMOS units are offered, via a CAD application, ST-SPICE, which includes versions for deep-submicron fully-depleted mesa-isolated SOI CMOS units and exact goal SOI units together with polysilicon TFTs.
CMOS VLSI Engineering: Silicon-On-Insulator is written for undergraduate senior scholars and first-year graduate scholars attracted to CMOS VLSI. it's going to even be appropriate for electric engineering pros attracted to microelectronics.

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Extra resources for CMOS VLSI Engineering: Silicon-on-Insulator (SOI)

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1104-1110, 1995 (in Japanese). [5] B. Davari, R. H. Dennard, and G. G. , Vol. 4, pp. 595-606, Apr. 1995. [6] S. Cristoloveanu and S. Li, "Electrical Characterization of Silicon-on-Insulator Materials and Devices," Kluwer Academic: Boston, 1995. [7] S. Ohr, "GaAs Finds Home in Wireless & High-Speed Data-Communications Applications," Computer Design, pp. 59-68, March 1994. [8] G. G. Shahidi, T. H. Ning, T. 1. Chappell, J. H. Comfort, B. A. Chappell, R. Franch, C. J. Anderson, P. W. Cook, S. E. Schuster, M.

Therefore, device density of the bulk CMOS technology cannot be high. As shown in Fig. 5, for a deepsubmicron down-scaled bulk CMOS technology based on n-well or p-well, the increased substrate doping density may degrade the device performance. In addition, the parasitic npn and pnp BJTs in the well and the substrate may be accidentally turned on to cause latch-up. In contrast, in the SOl technology, owing to the buried oxide isolation, no latch-up exists. 1. WHAT IS SOl? 5: Cross section of bulk and SOl CMOS devices.

1 Evolution of the mainstream SOl Technology. 3 Parameters of the device under study. . . . 170 Parameters of the SOl NMOS device under study. 180 Parameters of the double-gate ultrathin SOl NMOS device under study. 1 Device parameters of the accumulation-mode SOl PMOS device under study. . . . . . . . . 1 Model parameters used in ST-SPICE. . 4 Device parameters of the a-Si:H TFT under study. n-channel TFT device parameters.. . . . . p-channel TFT device parameters..

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