By Benoit Nadeau-Dostie
Layout for AT-Speed try out, prognosis and size is the 1st booklet to supply functional and confirmed design-for-testability (DFT) suggestions to chip and process layout engineers, try engineers and product managers on the silicon point in addition to on the board and platforms degrees. Designers will see how the implementation of embedded attempt permits simplification of silicon debug and process bring-up. try out engineers will confirm how embedded attempt presents a fantastic point of at-speed try out, analysis and size with out exceeding the functions in their apparatus. Product managers will learn the way the time, assets and prices linked to try improvement, manufacture expense and lifecycle upkeep in their items will be considerably lowered via designing embedded try within the product. A entire layout circulate and research of the impression of embedded try on a layout makes this publication a `must learn' ahead of any DFT is tried.
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Extra resources for Design for AT-Speed Test, Diagnosis and Measurement (FRONTIERS IN ELECTRONIC TESTING Volume 15)
Example text
Logic BIST has an exclusive run-time programmable power-level feature that allows control of the average power without sacrificing at-speed testing. This is done by shifting most of the scan patterns at a programmable low speed and applying the last few shift cycles and the capture cycle at the maximum speed. Benefits In addition to the general benefits listed in the section defining BIST and applicable to all Logic Vision BIST technologies, the following benefits deserve specific mention for the logic BIST capability.
DFT Methods Used in Embedded Test 11 Figure 1-5 BScan Access Using the Five-Pin Tap Interface Essentially, boundary scan adds scannable logic cells to the pins of a chip. These BScan cells provide two test modes: Internal test mode—enables control and observation of the internal functions of the chip via the boundary-scan cells. The internal circuitry is tested while the chip is isolated from external pins. External test mode—enables control and observation of the pins of the chip via the boundaryscan cells.
During the normal operation of the circuit, asynchronous interfaces are designed to transfer data between clock domains to ensure that clock skew is not an issue. During scan, the entire circuit is operated in a way that all clock sources are driven from a single test clock, or derivatives of that clock, and the functional asynchronous interfaces are disabled. In this case, clock skew can make transferring data between flip-flops of different clock domains unreliable by causing hold-time violations.