By Ban Wong, Anurag Mittal, Yu Cao, Greg W. Starr
In keeping with the authors' expansive choice of notes taken through the years, Nano-CMOS Circuit and actual layout bridges the distance among actual and circuit layout and fabrication processing, manufacturability, and yield. This leading edge ebook covers: technique expertise, together with sub-wavelength optical lithography; influence of technique scaling on circuit and actual implementation and coffee energy with leaky transistors; and DFM, yield, and the impression of actual implementation.
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Cobalt is typically capped with titanium or TiN during the blanket metal deposition to protect it from oxidation. The cap is then removed during the selective etch between RTP1 and RTP2. Scaling limitations of cobalt silicide are seen below 50-nm line widths and are driving the industry to shift to nickel silicide. NiSi maintains low sheet resistance below 30-nm line widths [56]. 10. However, this results in excessive silicidation of narrow lines, indicated by a decrease in sheet resistance versus gate length below 100 nm.
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