By Ming?Dou Ker, Sheng?Fu Hsu(auth.)
Content material:
Chapter 1 advent (pages 1–21):
Chapter 2 actual Mechanism of TLU below the System?Level ESD try out (pages 23–45):
Chapter three Component?Level size for TLU lower than System?Level ESD issues (pages 47–73):
Chapter four TLU Dependency on Power?Pin Damping Frequency and Damping think about CMOS built-in Circuits (pages 75–93):
Chapter five TLU in CMOS ICs within the electric speedy brief try out (pages 95–112):
Chapter 6 technique on Extracting Compact structure principles for Latchup Prevention (pages 113–150):
Chapter 7 particular structure concerns for Latchup Prevention (pages 151–168):
Chapter eight TLU Prevention in Power?Rail ESD Clamp Circuits (pages 169–206):
Chapter nine precis (pages 207–210):
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Transient-Induced Latchup in CMOS Integrated Circuits
Content material: bankruptcy 1 creation (pages 1–21): bankruptcy 2 actual Mechanism of TLU less than the process? point ESD attempt (pages 23–45): bankruptcy three part? point dimension for TLU lower than process? point ESD issues (pages 47–73): bankruptcy four TLU Dependency on energy? Pin Damping Frequency and Damping think about CMOS built-in Circuits (pages 75–93): bankruptcy five TLU in CMOS ICs within the electric quick temporary try (pages 95–112): bankruptcy 6 technique on Extracting Compact structure ideas for Latchup Prevention (pages 113–150): bankruptcy 7 exact format concerns for Latchup Prevention (pages 151–168): bankruptcy eight TLU Prevention in energy?
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Additional resources for Transient-Induced Latchup in CMOS Integrated Circuits
Example text
20. 20 Total stored minority carriers, QStored, causing ISb (tA t tB) inside the N-well region. The inset figure is an ideal 1-D diode used for deriving the 1-D analytical model of the averaged ISb (IAve) [7, 8]. (Reprinted with permission from IEEE). 3), IAve can be further simplified as follows: IAve QStored QStored ¼ tB À tA ð1=DFreq Þ=4 X 0 À Xn qVðtA Þ qVðtB Þ ni 2 À nL kT kT P ¼ 4DFreq q LP 1 À e Àe e ND VðtB Þ qVðtA Þ qVðtB Þ À 2:5 ¼ Z DFreq e kT . . e kT ¼ e kT=q ¼ e 0:0259 ffi 0 where: X 0 À Xn ni 2 À nL P Z ¼ 4q LP 1 À e ND ð2:4Þ ð2:5Þ is a constant and independent on the damping frequency (DFreq), applied voltage amplitude (VP), and damping factor (DFactor).
17–19. R. P. (1983) A transient analysis of latchup in bulk CMOS. IEEE Transactions on Electron Devices, 30, 170–179. Y. (1985) Transient latchup in bulk CMOS with a voltage-dependent well-substrate junction capacitance. IEEE Transactions on Electron Devices, 32, 717–720. [15] EIA/JEDEC (2006) Standard No. 7A, IC Latch-up Test, Electronic Industries Association. -D. -Y. (2003) Methodology on extracting compact layout rules for latchup prevention in deepsubmicron bulk CMOS technology. IEEE Transactions on Semiconductor Manufacturing, 16, 319–334.
Et al. (2005) Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, 27th Conference, pp. 126–130. 4-2004, Transient Latch-up Testing–Component Level Supply Transient Stimulation, ESD Association Standard Practice. [27] EIA/JEDEC (2006) Standard No. 78A, IC Latch-up Test, Electronic Industries Association. -D. -F. (2004) Transient-induced latchup in CMOS technology: physical mechanism and device simulation, International Electron Devices Meeting Technical Digest, IEEE, New York, NY, USA, pp.