Download Electrothermal Analysis Of Vlsi Systems by Yi-Kan Cheng, Ching-Han Tsai, Chin-Chi Teng, Sung-Mo (Steve) PDF

By Yi-Kan Cheng, Ching-Han Tsai, Chin-Chi Teng, Sung-Mo (Steve) Kang

Electrothermal research of VLSI structures addresses electrothermal difficulties in glossy VLSI platforms. half I, The construction Blocks, discusses electrothermal phenomena and the basic construction blocks that electrothermal simulation calls for (including energy research, temperature-dependent gadget modeling, thermal/electrothermal simulation, and experimental setup-calibration). half II, The functions, discusses 3 very important functions of VLSI electrothermal research together with temperature-dependent electromigration prognosis, cell-level thermal placement and temperature-driven strength and timing research. Electrothermal research of VLSI platforms could be worthy for researchers within the fields of IC reliability research and actual layout, in addition to VLSI designers and graduate scholars.

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A. , Essentials of Pade Approximants. New York, N Y Academic Press, 1975. [8] C. H. Diaz, S. M. Kang, and C. Duvvury, “Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 482-493, Apr. 1994. [9] C. H. Diaz and S. M . Kang, “New algorithms for circuit simulation of device breakdown,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.

For VLSI/ULSI chips with complex packaging structures, the simplified boundary conditions and 1-D/2-D approaches may not be valid. To handle this problem, a thermal simulation framework, iTEMP, has been built in ILLIADS-T to solve the 3-D heat equations for the chip substrate and to model the packages and heat sinks as effective thermal resistances. iTEMP can handle various thermal boundary conditions at any side of the chip with no limitations. A hierarchical approach was also developed in this thermal simulation framework in order to quickly identify the on-chip hot spots and to subsequently pinpoint the hot-spot temperatures.

This technique is clearly accurate because the inputs are known a priori. How the input vectors are collected and how many input sequences are needed to be representative are beyond the concerns of the deterministic technique. However, the input patterns can be generated exhaustively for all combination of possible input logic transitions when the total number of inputs is small, or are gathered for specific applications that are described by a sequence of architectural instructions. For the latter, it is often of great interest to provide the instructions that cause the maximum power (worst case).

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