By Frédéric Mallet, Charles André, Robert de Simone (auth.), Dominique Borrione (eds.)
More than ever, FDL is where for researchers, builders, designers, academia, and EDA device businesses to offer and to benefit concerning the newest medical achievements, functional purposes and clients reports within the area of specification and layout languages. FDL covers the modeling and layout equipment, and their most modern aiding instruments, for advanced embedded platforms, structures on chip, and heterogeneous systems.
FDL 2009 is the 12th in a sequence of occasions that have been held in every single place Europe, in chosen destinations well known for his or her Universities and Reseach associations in addition to the significance in their business surroundings in machine technological know-how and Micro-electronics. In 2009, FDL used to be prepared within the appealing south of France quarter of Sophia Antipolis. including the DASIP (Design and Architectures for sign and picture Processing) convention and an analogous (Sophia Antipolis MicroElectronics ) Forum.
All submitted papers have been rigorously reviewed to construct a application with 27 complete and 10 brief contributions. From those, this system Committee chosen a shorter checklist, in keeping with the reviews of the reviewers, and the originality and relevance of the paintings that was once offered on the discussion board. The revised, and occasionally prolonged models of those contributions represent the chapters of this volume.
Advances in layout equipment from Modeling Languages for Embedded platforms and SoC’s provides extensions to straightforward specification and outline languages, in addition to new language-based layout recommendations and methodologies to resolve the demanding situations raised by means of combined sign and multi-processor structures on a chip. it really is meant as a reference for researchers and teachers, in addition to a state-of-the-art milestone for designers and CAD developers.
Read or Download Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 PDF
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Additional info for Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009
Example text
The most important contributions exposing complete design flows merging Hw/Sw Co-design and MDE can be found within the Gaspard2 toolchain in [24, 36], where the authors present a chain generating a SystemC simulation tool targeting High Performance Embedded Systems (HPES) modelled using MARTE profile plus some extensions. Another interesting work bridging Codesign and MDE is the theoretical proposal of MoPCoM [16], in [23], where a design process leads to SystemC code generation from MARTE model specifications.
The framework is composed of a compiler-like system, with Front-end, Intermediate Representation (IR-XML) and Back-end. XSLT transformations are performed in order to map the XMI file created by the UML tool into a standardized XML format (front-end) and then from such format to the identified SystemC template (back-end). The produced simulators is made of modular SystemC code. e. SC MODULEs in the code) are bound to different State Machines Diagrams in the model. In case a State Machines Diagram contains more FSMs (parallel components or hierarchical separation), each FSM is mapped to a SC METHOD inside the same SC MODULE.
This formalization and all its terms are directly mappable to diagrams and MARTE stereotypes. The main specification graphs A and F are described by means of Composite Structure Diagrams and Activity/State Machine Diagrams respectively. The components of the P set are defined as properties from MARTE::NFP subprofile. g. ). 1. Co-design Analysis A Hw/Sw Co-design Analysis is performed to select an optimal implementation after the design phase has been completed. Although this work is not for studying in depth co-design algorithms, it is worth giving a subtle remark on how those algorithms are reached by our UML/MARTE Model.